Phase alignment is a commonly used technique among designers. Digital phase alignment comprises aligning the edges (rising or falling) of two square wave signals with equal (or integer multiple) frequencies with an arbitrary phase offset. In this case, phase may be characterized as a fraction of signal period given in terms of percent, degrees, or radians. Typically, the phase offsets obtained in digital phase alignment comprise a range of discrete values (for example 0, 45, 90 degrees) but this range can also include other non-discrete values or amounts.
As recognized by the present inventors, there may be situations that require fast alignment of two or more signals, such as clock signals. FIG. 1 shows an example of two synchronous clock signals, CLK1 and CLK2 (from the top), with a fast clock CLK3 shown below. The CLK3 frequency may be an integer multiple greater than the sequence of the CLK1 or CLK2 signals (for example 10×).
One conventional phase alignment approach is to use a counter that measures the time delay from the rising edge of CLK1 to CLK2, using CLK3 cycles. CLK1 is advanced according to the number of CLK3 cycles accumulated. A disadvantage of this solution is that a substantial number of CLK3 cycles may need to be counted from the beginning of the phase alignment operation, making the process take up to one CLK1 cycle to complete, which may render this solution impractical.
A second conventional phase alignment approach is to use a delay lock loop (DLL) to re-align the edges of the two clocks. The disadvantage of the DLL solution is that it is much slower achieving phase alignment, requiring several CLK1 cycles to maintain loop stability.
As recognized by the present inventors, what is needed is a method and system for alignment of two or more signals in a rapid manner, such as in a time period less than 1 clock cycle of the CLK1 or CLK2 signals.
It is against this background that various embodiments of the present invention were developed.